1. Technical Field
The present invention relates to a semiconductor cell and a method of forming the same, and more particularly, to a semiconductor cell including a horizontal air gap disposed at a lower portion of a sidewall of a storage node contact plug.
2. Related Art
Most electric appliances include semiconductor devices. Semiconductor devices include electric elements such as transistors, resistors, capacitors and the like. The electric elements are designed to perform partial functions of the electric appliances and are integrated on a semiconductor substrate. For example, electronic appliances such as computers or digital cameras include memory chips for storing information and processing chips for controlling the information, and the memory chips and processing chips include the electric elements integrated on a semiconductor substrate.
On the other hand, semiconductor devices need to be more highly integrated to satisfy user demands for good performance and low price. As the integration degree of semiconductor devices increases, the design rule is scaled down and patterns of the semiconductor devices become fine. As semiconductor devices become extra miniaturizated and more highly integrated, although total chip area increases in proportion to the increase in memory capacity, a cell area where patterns of semiconductor devices are formed is substantially reduced. Since the number of patterns formed in the limited cell area must be maximized to ensure the desired memory capacity, fine patterns having a reduced critical dimension have to be formed.
On the other hand, semiconductor devices are designed to fit specific purposes by implanting impurities into a silicon wafer or depositing a new material on the silicon wafer, or the like. The semiconductor devices include many elements such as transistors, capacitors, or resistors and the elements are connected to each other to receive or transmit data or signals.
In order to improve the integrity of a semiconductor device, dimensions of components within the semiconductor device have to be scaled down, and lengths and widths of interconnections have to be reduced. For example, a word line for transferring a control signal and a bit line for transferring data are used as interconnections within a semiconductor memory device. When widths or cross-sectional sizes of the word line and the bit line are reduced, resistance, which interrupts the transmission of the control signal or data, is increased. Such increased resistance deteriorates transmission speed of signals or data within the semiconductor device, increases power consumption, and further damages operation stability of the semiconductor memory device.
In contrast, when the widths of the word line and the bit line are maintained to be as large as in the related art to prevent increase in the resistance, the physical distance between adjacent word lines or between bit lines becomes closer. In this case, when a spacer is formed to electrically isolate the bit line and the storage node contact plug, a coupling effect between the bit line and the storage node contact plug increases and the coupling effect causes parasitic capacitance of the bit line to increase, thereby deteriorating sensing capability. This disturbs the data and prevents it from being smoothly transferred through the bit line. Thus the semiconductor memory device cannot output data stored in a unit cell.
A method has been proposed to increase amounts of charges corresponding to data output from the unit cell in order to solve the problem due to the increase of the parasitic capacitance in the bit line, but a size of a capacitor within a unit cell of a semiconductor memory device has to be increased to obtain this result. However, as the integrity of the semiconductor memory device increases, an area occupied by the capacitor within the semiconductor memory device shrinks. That is, there is a limit to increasing the size of the capacitor within a unit cell in a highly integrated semiconductor memory device.